An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs

An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2015-12, Vol.62 (12), p.2817-2828
Main Authors: Kwon, Soon-Won, Lee, Joon-Yeong, Lee, Jinhee, Han, Kwangseok, Kim, Taeho, Lee, Sangeun, Lee, Jeong-Sup, Yoon, Taehun, Won, Hyosup, Park, Jinho, Bae, Hyeon-Min
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Algorithms
Automatic control
Bandwidth
Bang-bang PLL
CDR
Clocks
CMOS
Control theory
Correlation
Delay
Gain
Gain control
Jitter
kalman gain
Mathematical analysis
Optimization
Random sequences
serial links
serial-in/serial-out
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 μm × 170 μm.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2015.2495725