COTS-Based High-Performance Computing for Space Applications

Commercial-off-the-shelf devices are often advocated as the only solution to the increasing performance requirements in space applications. This paper presents the solutions developed in the frame of the European Space Agency's HiRel program, concluded in December 2014, where a number of techni...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2015-12, Vol.62 (6), p.2687-2694
Main Authors: Esposito, S., Albanese, C., Alderighi, M., Casini, F., Giganti, L., Esposti, M. L., Monteleone, C., Violante, M.
Format: Article
Language:English
Subjects:
Central Processing Unit
Central processing unit (CPU)
commercial off the shelf (COTS)
fault injection
Fault tolerance
memory encoding
memory protection
Single event upsets
single-event upset (SEU)
software-implemented fault tolerance (SIFT)
space applications
Space missions
watchdog processor
watchdog timer
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Commercial-off-the-shelf devices are often advocated as the only solution to the increasing performance requirements in space applications. This paper presents the solutions developed in the frame of the European Space Agency's HiRel program, concluded in December 2014, where a number of techniques proposed in the past 10 years have been used to design a highly reliable system, which has been selected for forthcoming space missions. This paper presents the system architecture, describes performed evaluations, and discusses the results.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2015.2492824