Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characteriza...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2016-02, Vol.35 (2), p.220-231
Main Authors: Posser, Gracieli, Mishra, Vivek, Jain, Palkesh, Reis, Ricardo, Sapatnekar, Sachin S.
Format: Article
Language:English
Subjects:
Benchmarking
Cell-internal Signal Electromigration
Circuits
Computer aided design
Current density
Current Divergence
Design engineering
Discharges (electric)
EDA
Electromigration
Heating
Interconnections
Joule Heating
Metals
Optimization
Physical Design
Rails
Wires
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Summary:Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2015.2456427