A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

• Published in: IEEE journal of solid-state circuits 2016-02, Vol.51 (2), p.428-439
• Main Authors: Guanghua Shu, Woo-Seok Choi, Saxena, Saurabh, Talegaonkar, Mrunmay, Anand, Tejasvi, Elkholy, Ahmed, Elshazly, Amr, Hanumolu, Pavan Kumar
• Format: Article
• Language: English
• Subjects: Active repeater; automatic frequency acquisition; Automatic frequency control; continuous-rate receivers; decouple jitter transfer (JTRAN)/jitter generation (JGEN); decouple JTRAN/jitter tolerance (JTOL); Detectors; digital clock and data recovery (CDR); fractional-N phase-locked loop (PLL); Frequency locked loops; high-speed serial link; Jitter; jitter peaking; multiplying delay-locked loop; optical links; Oscillators; Phase locked loops; reference-less frequency-locked loop; supply regulator; wide-range digitally controlled oscillator (DCO)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2497963

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang-bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER