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Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices
This paper reviews the bevel-edge termination techniques for silicon carbide (SiC) power devices, such as bevel junction termination extension (JTE), resistive-bevel termination, bevel-assisted JTE, and positive-bevel termination. The proposed bevel-edge termination techniques significantly reduce t...
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Published in: | IEEE transactions on electron devices 2016-04, Vol.63 (4), p.1630-1636 |
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Main Authors: | , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | This paper reviews the bevel-edge termination techniques for silicon carbide (SiC) power devices, such as bevel junction termination extension (JTE), resistive-bevel termination, bevel-assisted JTE, and positive-bevel termination. The proposed bevel-edge termination techniques significantly reduce the chip size for SiC power devices. PiN diodes and test structures were fabricated to quantify the relative performance of the proposed structures. Quantitative comparison in chip size reduction, process schemes, and future research directions is discussed in detail. |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2016.2532602 |