Trigger-Centric Loop Mapping on CGRAs

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2016-05, Vol.24 (5), p.1998-2002
• Main Authors: Yin, Shouyi, Zhou, Pengcheng, Liu, Leibo, Wei, Shaojun
• Format: Article
• Language: English
• Subjects: Acceleration; Branch; coarse-grained reconfigurable architectures (CGRAs); compilation; Digital signal processors; Kernel; loop pipelining; Merging; modulo scheduling; Redundancy; Registers; Time complexity; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2486781

A coarse-grained reconfigurable architecture (CGRA) is a promising platform based on considerations for both performance and power efficiency. One of the primary obstacles that CGRAs might face is how to accelerate loops with if-then-else (ITE) structures. A recent control paradigm for CGRAs named triggered instruction architecture (TIA) can provide an efficient scheme to accelerate loops with ITE structures. Yet common loop mapping frameworks cannot leverage this scheme autonomously. To this end, this brief makes two contributions: 1) identify and remove redundancy nodes from a data flow graph and 2) propose an integrated approach-TRMap, which consists of operations merging, Boolean operations offloading, and transformation of triggers. Our experimental results from some vital kernels extracted from SPEC2006 benchmarks and digital signal processing applications show that by using TIA scheme, TRMap is able to accelerate loops with ITE structures to an execution that is 1.38× and 1.64× faster than that achieved by a full predication scheme (FP-Choi) and a state-of-the-art method (BRMap).