Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they hav...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2016-03, Vol.63 (3), p.1041-1046
Main Authors: Kwon, Dae Woong, Kim, Wandong, Kim, Do-Bin, Lee, Sang-Ho, Seo, Joo Yun, Baek, Myung-Hyun, Park, Ji-Ho, Choi, Eunseok, Cho, Gyu Seong, Park, Sung-Kye, Lee, Jong-Ho, Park, Byung-Gook
Format: Article
Language:English
Subjects:
Arrays
Channels
Decision support systems
Devices
Disturbances
Dummies
Electric potential
Equivalent circuits
Gates
Leakage currents
Logic gates
Multilevel
Reliability
Stress
Threshold voltage
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Summary:Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2016.2517336