InAs FinFETs With [Formula Omitted] nm Fabricated Using a To-Down Etch Process

We report the first demonstration of InAs FinFETs with fin width [Formula Omitted] in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height [Formula Omitted] nm controlled by the use of an etch stop layer incorporate...

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Bibliographic Details
Published in:IEEE electron device letters 2016-03, Vol.37 (3), p.261
Main Authors: Oxland, R, X Li, Chang, S W, Wang, S W, Vasen, T, Ramvall, P, Contreras-Guerrero, R, Rojas-Ramirez, J, Holland, M, Doornbos, G, Chang, Y S, Macintyre, D S, Thoms, S, Droopad, R, Y-C, Yeo, Diaz, C H, Thayne, I G, Passlack, M
Format: Article
Language:English
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Summary:We report the first demonstration of InAs FinFETs with fin width [Formula Omitted] in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height [Formula Omitted] nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length [Formula Omitted], peak transconductance [Formula Omitted] is measured at [Formula Omitted] V demonstrating that electron transport in InAs fins can match planar devices.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2016.2521001