An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors

• Published in: IEEE transactions on electron devices 2016-09, Vol.63 (9), p.3599-3604
• Main Authors: Kim, Min-Kyu, Hong, Seong-Kwan, Kwon, Oh-Kyong
• Format: Article
• Language: English
• Subjects: Analog-digital conversion; Calibration; Capacitors; CMOS; CMOS image sensor (CIS); CMOS image sensors; column-parallel readout; Digital to analog converters; Generators; hybrid analog-to-digital converter (ADC); Noise; Nonlinearity; Power demand; Sensors; single-slope (SS) ADC; successive approximation ADC; Timing
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2587721

This paper presents an area-efficient and low-power 12-b successive approximation register/single-slope analog-todigital converter (SAR/SS ADC) for CMOS image sensor (CIS) applications. The number of unit capacitors of the proposed SAR/SS ADC is reduced to 1/64th of that of a conventional 12-b SAR ADC using only a 6-b capacitor digital-to-analog converter (DAC) and the power consumption is reduced by sharing analog circuits between the SAR ADC and the SS ADC. In addition, the proposed ADC properly operates without using any calibration method as it is designed to be robust to inaccuracies in analog circuits by connecting the ramp signal to the bottom plate of the unit capacitor in the capacitor DAC. A 1936 × 840 pixel 60 frames/s CIS with the proposed SAR/SS ADCs was fabricated using a 90-nm CMOS process, and each readout channel with the proposed SAR/SS ADC occupies an area of 2.24 μm × 998 μm and consumes a power of 30 μW. The measurement results show that the SAR/SS ADC has a differential nonlinearity of -0.45/+0.84 LSB and an integral nonlinearity of -1.5/+0.74 LSB. In addition, the developed CIS has a temporal noise of 2.7 LSB rms and a column fixed pattern noise of 0.07 LSB.