A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS

This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, ba...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2016-10, Vol.63 (10), p.1746-1757
Main Authors: Fei Lu, Rui Ma, Zongyu Dong, Li Wang, Chen Zhang, Chenkun Wang, Qi Chen, Wang, X. Shawn, Feilong Zhang, Cheng Li, He Tang, Yuhua Cheng, Wang, Albert
Format: Article
Language:English
Subjects:
Behavioral modeling
CMOS
co-design
Electrostatic discharges
ESD
Integrated circuit modeling
Logic gates
Semiconductor device modeling
Thyristors
Transient analysis
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Summary:This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2581839