Loading…
A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter
This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over tim...
Saved in:
Published in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2016-10, Vol.63 (10), p.1639-1651 |
---|---|
Main Authors: | , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | cdi_FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3 |
---|---|
cites | cdi_FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3 |
container_end_page | 1651 |
container_issue | 10 |
container_start_page | 1639 |
container_title | IEEE transactions on circuits and systems. I, Regular papers |
container_volume | 63 |
creator | Tzu-Fan Wu Dey, Sourya Chen, Mike Shuo-Wei |
description | This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, adapts its sampling rate according to the incoming signal, and interfaces seamlessly with synchronous digital processers. In addition, the proposed ADC architecture relaxes voltage quantization by introducing time quantization, which favors future technology scaling. Furthermore, approximated analytical noise models are derived to study the underlying quantization effects on the proposed digital AA filter. It explores the theoretical bounds of achievable signal-to-noise ratio (SNR) given different ADC and filter design parameters. Finally, some hardware design considerations and limitations are discussed. |
doi_str_mv | 10.1109/TCSI.2016.2586523 |
format | article |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_1831005656</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7571162</ieee_id><sourcerecordid>4223940571</sourcerecordid><originalsourceid>FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3</originalsourceid><addsrcrecordid>eNo9kEFLwzAUx4MoOKcfQLwEPLfmJUuaHEvndDAU3GTH0KbpltG1M00PfntbNry8_zv8_u_BD6FHIDEAUS-bbL2MKQERUy4Fp-wKTYBzGRFJxPW4z1QkGZW36K7rDoRQRRhM0DbFH23TN65q_RGv8-Opds0Op_MMp97sXbAm9N7irQt7_GVN21Ru1_u8qC2eu50LeY3TJrgorV3ejdWFq4P19-imyuvOPlxyir4Xr5vsPVp9vi2zdBUZxkSIrCmIYIKaWSklYdIWZcVKVQJhw6iY4klibFJSxYwyUhWCiHzGEw4gBQzAFD2f7558-9PbLuhD2_tmeKlBMiCECy4GCs6U8W3XeVvpk3fH3P9qIHr0p0d_evSnL_6GztO546y1_3zCEwBB2R-m2WrZ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1831005656</pqid></control><display><type>article</type><title>A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Tzu-Fan Wu ; Dey, Sourya ; Chen, Mike Shuo-Wei</creator><creatorcontrib>Tzu-Fan Wu ; Dey, Sourya ; Chen, Mike Shuo-Wei</creatorcontrib><description>This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, adapts its sampling rate according to the incoming signal, and interfaces seamlessly with synchronous digital processers. In addition, the proposed ADC architecture relaxes voltage quantization by introducing time quantization, which favors future technology scaling. Furthermore, approximated analytical noise models are derived to study the underlying quantization effects on the proposed digital AA filter. It explores the theoretical bounds of achievable signal-to-noise ratio (SNR) given different ADC and filter design parameters. Finally, some hardware design considerations and limitations are discussed.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2016.2586523</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analog-to-digital converter ; anti-aliasing filter ; Bandwidth ; Computer architecture ; Harmonic analysis ; level-crossing ; Nonuniform sampling ; Quantization (signal) ; quantization noise ; Signal processing algorithms ; Signal to noise ratio</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2016-10, Vol.63 (10), p.1639-1651</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3</citedby><cites>FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3</cites><orcidid>0000-0002-7139-4524</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7571162$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Tzu-Fan Wu</creatorcontrib><creatorcontrib>Dey, Sourya</creatorcontrib><creatorcontrib>Chen, Mike Shuo-Wei</creatorcontrib><title>A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, adapts its sampling rate according to the incoming signal, and interfaces seamlessly with synchronous digital processers. In addition, the proposed ADC architecture relaxes voltage quantization by introducing time quantization, which favors future technology scaling. Furthermore, approximated analytical noise models are derived to study the underlying quantization effects on the proposed digital AA filter. It explores the theoretical bounds of achievable signal-to-noise ratio (SNR) given different ADC and filter design parameters. Finally, some hardware design considerations and limitations are discussed.</description><subject>Analog-to-digital converter</subject><subject>anti-aliasing filter</subject><subject>Bandwidth</subject><subject>Computer architecture</subject><subject>Harmonic analysis</subject><subject>level-crossing</subject><subject>Nonuniform sampling</subject><subject>Quantization (signal)</subject><subject>quantization noise</subject><subject>Signal processing algorithms</subject><subject>Signal to noise ratio</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><recordid>eNo9kEFLwzAUx4MoOKcfQLwEPLfmJUuaHEvndDAU3GTH0KbpltG1M00PfntbNry8_zv8_u_BD6FHIDEAUS-bbL2MKQERUy4Fp-wKTYBzGRFJxPW4z1QkGZW36K7rDoRQRRhM0DbFH23TN65q_RGv8-Opds0Op_MMp97sXbAm9N7irQt7_GVN21Ru1_u8qC2eu50LeY3TJrgorV3ejdWFq4P19-imyuvOPlxyir4Xr5vsPVp9vi2zdBUZxkSIrCmIYIKaWSklYdIWZcVKVQJhw6iY4klibFJSxYwyUhWCiHzGEw4gBQzAFD2f7558-9PbLuhD2_tmeKlBMiCECy4GCs6U8W3XeVvpk3fH3P9qIHr0p0d_evSnL_6GztO546y1_3zCEwBB2R-m2WrZ</recordid><startdate>201610</startdate><enddate>201610</enddate><creator>Tzu-Fan Wu</creator><creator>Dey, Sourya</creator><creator>Chen, Mike Shuo-Wei</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-7139-4524</orcidid></search><sort><creationdate>201610</creationdate><title>A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter</title><author>Tzu-Fan Wu ; Dey, Sourya ; Chen, Mike Shuo-Wei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Analog-to-digital converter</topic><topic>anti-aliasing filter</topic><topic>Bandwidth</topic><topic>Computer architecture</topic><topic>Harmonic analysis</topic><topic>level-crossing</topic><topic>Nonuniform sampling</topic><topic>Quantization (signal)</topic><topic>quantization noise</topic><topic>Signal processing algorithms</topic><topic>Signal to noise ratio</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tzu-Fan Wu</creatorcontrib><creatorcontrib>Dey, Sourya</creatorcontrib><creatorcontrib>Chen, Mike Shuo-Wei</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tzu-Fan Wu</au><au>Dey, Sourya</au><au>Chen, Mike Shuo-Wei</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2016-10</date><risdate>2016</risdate><volume>63</volume><issue>10</issue><spage>1639</spage><epage>1651</epage><pages>1639-1651</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, adapts its sampling rate according to the incoming signal, and interfaces seamlessly with synchronous digital processers. In addition, the proposed ADC architecture relaxes voltage quantization by introducing time quantization, which favors future technology scaling. Furthermore, approximated analytical noise models are derived to study the underlying quantization effects on the proposed digital AA filter. It explores the theoretical bounds of achievable signal-to-noise ratio (SNR) given different ADC and filter design parameters. Finally, some hardware design considerations and limitations are discussed.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2016.2586523</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-7139-4524</orcidid><oa>free_for_read</oa></addata></record> |
fulltext | fulltext |
identifier | ISSN: 1549-8328 |
ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2016-10, Vol.63 (10), p.1639-1651 |
issn | 1549-8328 1558-0806 |
language | eng |
recordid | cdi_proquest_journals_1831005656 |
source | IEEE Electronic Library (IEL) Journals |
subjects | Analog-to-digital converter anti-aliasing filter Bandwidth Computer architecture Harmonic analysis level-crossing Nonuniform sampling Quantization (signal) quantization noise Signal processing algorithms Signal to noise ratio |
title | A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T03%3A16%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Nonuniform%20Sampling%20ADC%20Architecture%20With%20Reconfigurable%20Digital%20Anti-Aliasing%20Filter&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20I,%20Regular%20papers&rft.au=Tzu-Fan%20Wu&rft.date=2016-10&rft.volume=63&rft.issue=10&rft.spage=1639&rft.epage=1651&rft.pages=1639-1651&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2016.2586523&rft_dat=%3Cproquest_cross%3E4223940571%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c336t-ecb06362c4d88038ebdf3d9d1039d1f39577ce7d293c9c89b606a4575118611f3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1831005656&rft_id=info:pmid/&rft_ieee_id=7571162&rfr_iscdi=true |