Statistical soft error rate estimation of combinational circuits using Bayesian networks

Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical metho...

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Bibliographic Details
Published in:Compel 2016-09, Vol.35 (5), p.1760-1773
Main Authors: Sabet, M. Amin, Ghavami, Behnam
Format: Article
Language:English
Subjects:
Accuracy
Algorithms
Bayesian analysis
Circuit design
CMOS
Computer simulation
Digital electronics
Electric power distribution
Electrical properties
Expected values
Integrated circuits
Logic
Masking
Methods
Monte Carlo simulation
Probability distribution
Propagation
Random variables
Simulation
Soft errors
Statistical analysis
Statistical methods
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Summary:Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.
ISSN:0332-1649
2054-5606
DOI:10.1108/COMPEL-09-2015-0317