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Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description
We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilo...
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Published in: | IEEE transactions on electron devices 2016-12, Vol.63 (12), p.4981-4985 |
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Main Authors: | , , , , , , |
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container_end_page | 4985 |
container_issue | 12 |
container_start_page | 4981 |
container_title | IEEE transactions on electron devices |
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creator | Pahwa, Girish Dutta, Tapas Agarwal, Amit Khandelwal, Sourabh Salahuddin, Sayeef Chenming Hu Chauhan, Yogesh Singh |
description | We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET. |
doi_str_mv | 10.1109/TED.2016.2614432 |
format | article |
fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_journals_1844102671</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7588064</ieee_id><sourcerecordid>1844102671</sourcerecordid><originalsourceid>FETCH-LOGICAL-c291t-be51ca2fc3285a8079132af3136a60b57093a40bc39cb436c36fde11a64cbea53</originalsourceid><addsrcrecordid>eNo9kU9r20AQxZfQQNw090IvCz3L2dldraTejJx_kMYhuGcxWo-cNbak7q5a8ln6ZSPVJqdheO_3BuYx9hXEHEAU1-ub5VwKMHNpQGslz9gM0jRLCqPNJzYTAvKkULm6YJ9D2I2r0VrO2L9Fi_u34ALHdsPL7tCjjfxnt6G9a7e8a_gTbTG6P8RLHDUXsbXE1x7bEYqd539dfOX3bvvKV09JOXhPbfwf9gGuhtgPkS9d09CkOtzzF5rwKSt5Rh_5w4_jUb6kYL3ro-vaL-y8wX2gq9O8ZL9ub9blffK4unsoF4-JlQXEpKYULMrGKpmnmIusACWxUaAMGlGnmSgUalFbVdhaK2OVaTYEgEbbmjBVl-z7Mbf33e-BQqx23eDHv4QKcq1BSJPB6BJHl_VdCJ6aqvfugP6tAlFNFVRjBdVUQXWqYES-HRFHRB_2LM1zYbR6BxGug-o</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1844102671</pqid></control><display><type>article</type><title>Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description</title><source>IEEE Xplore (Online service)</source><creator>Pahwa, Girish ; Dutta, Tapas ; Agarwal, Amit ; Khandelwal, Sourabh ; Salahuddin, Sayeef ; Chenming Hu ; Chauhan, Yogesh Singh</creator><creatorcontrib>Pahwa, Girish ; Dutta, Tapas ; Agarwal, Amit ; Khandelwal, Sourabh ; Salahuddin, Sayeef ; Chenming Hu ; Chauhan, Yogesh Singh</creatorcontrib><description>We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2016.2614432</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analytical models ; Capacitance ; Circuit design ; Compact modeling ; ferroelectric ; Ferroelectricity ; Field effect transistors ; Impact analysis ; Mathematical model ; MOSFET ; MOSFETs ; negative capacitance ; negative capacitance FET (NCFET) ; Semiconductor device modeling ; Temperature effects ; Transient analysis</subject><ispartof>IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.4981-4985</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-be51ca2fc3285a8079132af3136a60b57093a40bc39cb436c36fde11a64cbea53</citedby><cites>FETCH-LOGICAL-c291t-be51ca2fc3285a8079132af3136a60b57093a40bc39cb436c36fde11a64cbea53</cites><orcidid>0000-0003-2094-858X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7588064$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,27903,27904,54775</link.rule.ids></links><search><creatorcontrib>Pahwa, Girish</creatorcontrib><creatorcontrib>Dutta, Tapas</creatorcontrib><creatorcontrib>Agarwal, Amit</creatorcontrib><creatorcontrib>Khandelwal, Sourabh</creatorcontrib><creatorcontrib>Salahuddin, Sayeef</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><creatorcontrib>Chauhan, Yogesh Singh</creatorcontrib><title>Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.</description><subject>Analytical models</subject><subject>Capacitance</subject><subject>Circuit design</subject><subject>Compact modeling</subject><subject>ferroelectric</subject><subject>Ferroelectricity</subject><subject>Field effect transistors</subject><subject>Impact analysis</subject><subject>Mathematical model</subject><subject>MOSFET</subject><subject>MOSFETs</subject><subject>negative capacitance</subject><subject>negative capacitance FET (NCFET)</subject><subject>Semiconductor device modeling</subject><subject>Temperature effects</subject><subject>Transient analysis</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><recordid>eNo9kU9r20AQxZfQQNw090IvCz3L2dldraTejJx_kMYhuGcxWo-cNbak7q5a8ln6ZSPVJqdheO_3BuYx9hXEHEAU1-ub5VwKMHNpQGslz9gM0jRLCqPNJzYTAvKkULm6YJ9D2I2r0VrO2L9Fi_u34ALHdsPL7tCjjfxnt6G9a7e8a_gTbTG6P8RLHDUXsbXE1x7bEYqd539dfOX3bvvKV09JOXhPbfwf9gGuhtgPkS9d09CkOtzzF5rwKSt5Rh_5w4_jUb6kYL3ro-vaL-y8wX2gq9O8ZL9ub9blffK4unsoF4-JlQXEpKYULMrGKpmnmIusACWxUaAMGlGnmSgUalFbVdhaK2OVaTYEgEbbmjBVl-z7Mbf33e-BQqx23eDHv4QKcq1BSJPB6BJHl_VdCJ6aqvfugP6tAlFNFVRjBdVUQXWqYES-HRFHRB_2LM1zYbR6BxGug-o</recordid><startdate>201612</startdate><enddate>201612</enddate><creator>Pahwa, Girish</creator><creator>Dutta, Tapas</creator><creator>Agarwal, Amit</creator><creator>Khandelwal, Sourabh</creator><creator>Salahuddin, Sayeef</creator><creator>Chenming Hu</creator><creator>Chauhan, Yogesh Singh</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2094-858X</orcidid></search><sort><creationdate>201612</creationdate><title>Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description</title><author>Pahwa, Girish ; Dutta, Tapas ; Agarwal, Amit ; Khandelwal, Sourabh ; Salahuddin, Sayeef ; Chenming Hu ; Chauhan, Yogesh Singh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-be51ca2fc3285a8079132af3136a60b57093a40bc39cb436c36fde11a64cbea53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Analytical models</topic><topic>Capacitance</topic><topic>Circuit design</topic><topic>Compact modeling</topic><topic>ferroelectric</topic><topic>Ferroelectricity</topic><topic>Field effect transistors</topic><topic>Impact analysis</topic><topic>Mathematical model</topic><topic>MOSFET</topic><topic>MOSFETs</topic><topic>negative capacitance</topic><topic>negative capacitance FET (NCFET)</topic><topic>Semiconductor device modeling</topic><topic>Temperature effects</topic><topic>Transient analysis</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pahwa, Girish</creatorcontrib><creatorcontrib>Dutta, Tapas</creatorcontrib><creatorcontrib>Agarwal, Amit</creatorcontrib><creatorcontrib>Khandelwal, Sourabh</creatorcontrib><creatorcontrib>Salahuddin, Sayeef</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><creatorcontrib>Chauhan, Yogesh Singh</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE/IET Electronic Library</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Pahwa, Girish</au><au>Dutta, Tapas</au><au>Agarwal, Amit</au><au>Khandelwal, Sourabh</au><au>Salahuddin, Sayeef</au><au>Chenming Hu</au><au>Chauhan, Yogesh Singh</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2016-12</date><risdate>2016</risdate><volume>63</volume><issue>12</issue><spage>4981</spage><epage>4985</epage><pages>4981-4985</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2016.2614432</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0003-2094-858X</orcidid></addata></record> |
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subjects | Analytical models Capacitance Circuit design Compact modeling ferroelectric Ferroelectricity Field effect transistors Impact analysis Mathematical model MOSFET MOSFETs negative capacitance negative capacitance FET (NCFET) Semiconductor device modeling Temperature effects Transient analysis |
title | Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance-Part I: Model Description |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T12%3A42%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Analysis%20and%20Compact%20Modeling%20of%20Negative%20Capacitance%20Transistor%20with%20High%20ON-Current%20and%20Negative%20Output%20Differential%20Resistance-Part%20I:%20Model%20Description&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Pahwa,%20Girish&rft.date=2016-12&rft.volume=63&rft.issue=12&rft.spage=4981&rft.epage=4985&rft.pages=4981-4985&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2016.2614432&rft_dat=%3Cproquest_ieee_%3E1844102671%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c291t-be51ca2fc3285a8079132af3136a60b57093a40bc39cb436c36fde11a64cbea53%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1844102671&rft_id=info:pmid/&rft_ieee_id=7588064&rfr_iscdi=true |