A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

A 1.2 V 20 nm 307 GB/s high-bandwidth memory (HBM) DRAM is presented to satisfy a high-bandwidth requirement of high-performance computing application. The HBM is composed of buffer die and multiple core dies, and each core die has 8 Gb DRAM cell array with additional 1 Gb ECC array. At-speed wafer...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2017-01, Vol.52 (1), p.250-260
Main Authors: Sohn, Kyomin, Yun, Won-Joo, Oh, Reum, Oh, Chi-Sung, Seo, Seong-Young, Park, Min-Sang, Shin, Dong-Hak, Jung, Won-Chang, Shin, Sang-Hoon, Ryu, Je-Min, Yu, Hye-Seung, Jung, Jae-Hun, Lee, Hyunui, Kang, Seok-Yong, Sohn, Young-Soo, Choi, Jung-Hwan, Bae, Yong-Cheol, Jang, Seong-Jin, Jin, Gyoyoung
Format: Article
Language:English
Subjects:
Adaptive refresh
at-speed wafer level test
Bandwidth
Computer architecture
Dynamic random access memory
high-bandwidth memory (HBM) DRAM
microbump IO
Microprocessors
Random access memory
Temperature distribution
Temperature sensors
Through-silicon vias
TSV
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Summary:A 1.2 V 20 nm 307 GB/s high-bandwidth memory (HBM) DRAM is presented to satisfy a high-bandwidth requirement of high-performance computing application. The HBM is composed of buffer die and multiple core dies, and each core die has 8 Gb DRAM cell array with additional 1 Gb ECC array. At-speed wafer level, a u-bump IO test scheme and an adaptive refresh scheme considering temperature distribution are proposed to guarantee test coverage and stable operation in a power-efficient manner.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2016.2602221