High-Bandwidth Memory (HBM) Test Challenges and Solutions

TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by JEDEC's HBM standard. This article is a written version of Jun's very interesting presentation at 3D-TEST 2015 on how such DRAM stacks are tested at SK hynix.

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Bibliographic Details
Published in:IEEE design and test 2017-02, Vol.34 (1), p.16-25
Main Authors: Jun, Hongshin, Nam, Sangkyun, Jin, Hanho, Lee, Jong-Chern, Park, Yong Jae, Lee, Jae Jin
Format: Magazinearticle
Language:English
Subjects:
Bandwidth allocation
Ports (Computers)
Random access memory
Stacking
Stress
Through-silicon vias
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Description
Summary:TSV-based 3-D stacking enables large-capacity, power-efficient DRAMs with high bandwidth, such as specified by JEDEC's HBM standard. This article is a written version of Jun's very interesting presentation at 3D-TEST 2015 on how such DRAM stacks are tested at SK hynix.
ISSN:2168-2356
2168-2364
DOI:10.1109/MDAT.2016.2624283