Cost-efficient design of a quantum multiplier–accumulator unit

• Published in: Quantum information processing 2017-01, Vol.16 (1), p.1-38, Article 30
• Main Author: Babu, Hafiz Md. Hasan
• Format: Article
• Language: English
• Subjects: Data Structures and Information Theory; Design improvements; Mathematical Physics; Physics; Physics and Astronomy; Quantum Computing; Quantum Information Technology; Quantum Physics; Spintronics
• ISSN: 1570-0755; 1573-1332
• DOI: 10.1007/s11128-016-1455-0

This paper proposes a cost-efficient quantum multiplier–accumulator unit. The paper also presents a fast multiplication algorithm and designs a novel quantum multiplier device based on the proposed algorithm with the optimum time complexity as multiplier is the major device of a multiplier–accumulator unit. We show that the proposed multiplication technique has time complexity O ( ( 3 log 2 n ) + 1 ) , whereas the best known existing technique has O ( n log 2 n ) , where n is the number of qubits. In addition, our design proposes three new quantum circuits: a circuit representing a quantum full-adder, a circuit known as quantum ANDing circuit, which performs the ANDing operation and a circuit presenting quantum accumulator. Moreover, the proposed quantum multiplier–accumulator unit is the first ever quantum multiplier–accumulator circuit in the literature till now, which has reduced garbage outputs and ancillary inputs to a great extent. The comparative study shows that the proposed quantum multiplier performs better than the existing multipliers in terms of depth, quantum gates, delays, area and power with the increasing number of qubits. Moreover, we design the proposed quantum multiplier–accumulator unit, which performs better than the existing ones in terms of hardware and delay complexities, e.g., the proposed ( n × n )—qubit quantum multiplier–accumulator unit requires O ( n 2 ) hardware and O ( log 2 n ) delay complexities, whereas the best known existing quantum multiplier–accumulator unit requires O ( n 3 ) hardware and O ( ( n - 1 ) 2 + 1 + n ) delay complexities. In addition, the proposed design achieves an improvement of 13.04, 60.08 and 27.2% for 4 × 4 , 7.87, 51.8 and 27.1% for 8 × 8 , 4.24, 52.14 and 27% for 16 × 16 , 2.19, 52.15 and 27.26% for 32 × 32 and 0.78, 52.18 and 27.28% for 128 × 128 -qubit multiplications over the best known existing approach in terms of number of quantum gates, ancillary inputs and garbage outputs, respectively. Moreover, on average, the proposed design gains an improvement of 5.62% in terms of area and power consumptions over the best known existing approach.