DESIGN OF LOW-POWER ADDER USING DOUBLE GATE & MTCMOS TECHNOLOGY

• Published in: Journal of Theoretical and Applied Information Technology 2017-01, Vol.95 (1), p.78
• Main Authors: Priyanka, K, Nehru, K, Rambabu, S, Kumaravelu, Nandeesh Kumar
• Format: Article
• Language: English
• ISSN: 1817-3195

Low power, high speed Dynamic adders is widely used in Digital Logic Designs to overcome the leakage power and speed issues in static adders. Hence, by using MTCMOS Technology, low power dynamic MTCMOS 8-Bit full-adder cells have been proposed. Eight bit MTCMOS adder circuit has been designed using 45nm CMOS Technology. The static Adder circuit is modified by adding an NMOS transistor as a footer or tail to the circuit. This tail transistor when operates in sleep mode, it cuts off the path of current flow from Rail to Rail, which results in leakage power reduction. Hence, the proposed double-gate, MTCMOS Technology dynamic adders are significantly faster as compared to static CMOS logic designs in two aspects reduction of delay when tail transistor operates in normal mode and reduction of leakage power when tail transistor operates in sleep mode. Design analyses, and comparison results verify that the proposed circuits operate with high speed, obtains a significant reduction in leakage power due to the tail transistor included in the circuit. It is also observed that the power consumption of proposed dynamic adder is significantly less compared to existing static adders.