Optimization of CMOS Repeater Driven Interconnect RC Line Using Genetic Algorithm

In this work, optimization of complementary metal oxide semiconductor(CMOS) repeater driven interconnect resistive-capacitive(RC) line is carried out using genetic algorithm(GA). This work is aimed at powerdelay-product(PDP) minimization of RC interconnect at 180 nm technology node. The algorithm si...

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Bibliographic Details
Published in:Shanghai jiao tong da xue xue bao 2017-04, Vol.22 (2), p.167-172
Main Authors: Kaur, Jasmeet, Gill, Sandeep Singh, Kaur, Navneet
Format: Article
Language:English
Subjects:
Algorithms
Architecture
CMOS
Computer Science
Electrical Engineering
Engineering
Genetic algorithms
Life Sciences
Materials Science
Optimization
Repeaters
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Summary:In this work, optimization of complementary metal oxide semiconductor(CMOS) repeater driven interconnect resistive-capacitive(RC) line is carried out using genetic algorithm(GA). This work is aimed at powerdelay-product(PDP) minimization of RC interconnect at 180 nm technology node. The algorithm simultaneously optimizes the values of supply voltage, number of repeaters and repeater width for delay and PDP minimization.The accuracy of results obtained is verified by simulations from Cadence virtuoso tool. For delay minimization,comparison of GA results with previous results of the literature shows an improvement of 44.4% in the value of the optimal number of repeaters required. This improvement is obtained by increasing the repeater size, which also increases power dissipation, so a tradeoff has also been achieved in terms of PDP minimization. The comparison of PDP results obtained in this work, with the results at 70, 100, and 130 nm technologies from literature shows improvement in optimal number of repeaters required. The results of algorithm and simulations are in good agreement and demonstrate the validity of proposed algorithm.
ISSN:1007-1172
1995-8188
DOI:10.1007/s12204-017-1817-5