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Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) a...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2017-04, Vol.64 (4), p.847-857
Main Authors: Hao Cai, You Wang, De Barros Naviner, Lirida Alves, Weisheng Zhao
Format: Article
Language:English
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Summary:In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (V dd ) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome V dd scaling bottleneck, an efficient framework for V dd scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (V dd ,V BB ,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2621344