Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high...

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Bibliographic Details
Published in:Multimedia tools and applications 2017-06, Vol.76 (11), p.13197-13219
Main Authors: Sathish Shet, K., Aswath, A. R., Hanumantharaju, M. C., Gao, Xiao-Zhi
Format: Article
Language:English
Subjects:
Algorithms
Application specific integrated circuits
Circuit design
Computer Communication Networks
Computer peripherals
Computer Science
Computer simulation
Data Structures and Information Theory
Field programmable gate arrays
Gate arrays
Integrated circuits
Multimedia Information Systems
Pipelining (computers)
Power consumption
Real time
Reconfigurable hardware
Special Purpose and Application-Based Systems
Steganography
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Summary:The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher’s method.
ISSN:1380-7501
1573-7721
DOI:10.1007/s11042-016-3736-0