7‐2: Design of Highly Reliable Depletion‐Mode a‐IGZO TFT Gate Driving Circuit for 31‐in. 8K4K 287‐ppi TFT‐LCD

In this paper, high reliable a‐IGZO TFT gate driving circuit was designed. Series‐connected two‐transistor (STT) structure and dual low‐voltage‐level power signal (Vss) were used to solve the initial negative Vth of IGZO TFTs. Special pull‐down holding part was designed for wider Vth shift window du...

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Bibliographic Details
Published in:SID International Symposium Digest of technical papers 2017-05, Vol.48 (1), p.68-71
Main Authors: Shi, Long-Qiang, Chen, Shu-Jhih, Chou, Yi-Fang, Zeng, Li-Mei, Zeng, Mian, Wang, Tian-Hong, Chen, Ren-Lu, Liao, Cong-Wei, Lv, Xiao-Wen, Li, Wen-Ying, Liu, X, Lee, Chia-Yu
Format: Article
Language:English
Subjects:
8K4K
BCE IGZO
Circuit design
Control systems
Depletion
Design
Design engineering
Electric potential
Gate Driver
narrow border
Simulation
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Summary:In this paper, high reliable a‐IGZO TFT gate driving circuit was designed. Series‐connected two‐transistor (STT) structure and dual low‐voltage‐level power signal (Vss) were used to solve the initial negative Vth of IGZO TFTs. Special pull‐down holding part was designed for wider Vth shift window during panel operation. The Vth shift margin of this proposed GOA design is from ‐5V to +9V by using Eldo‐Spice simulation system. In addition, the pull‐up control part could also play a role to pull the Q node voltage down and it is helpful for narrow border design. Finally, a 31‐in. 8K4K 287‐ppi TFT‐LCD was successfully demonstrated based on the study above.
ISSN:0097-966X
2168-0159
DOI:10.1002/sdtp.11561