A SVPWM to Eliminate Common-Mode Voltage for Multilevel Inverters

This paper presents a new space vector pulse width modulation (SVPWM) to eliminate common-mode voltage (CMV) for multilevel inverters. The proposed SVPWM is performed in a new coordinate system, in which the converter voltage vectors have only integer entries and the absolute coordinate increment be...

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Bibliographic Details
Published in:Energies (Basel) 2017-05, Vol.10 (5), p.715
Main Authors: Tang, Xiongmin, Lai, Chengjing, Liu, Zheng, Zhang, Miao
Format: Article
Language:English
Subjects:
Computation
Electric potential
Inverters
Multilevel
Potassium channels (voltage-gated)
Pulse duration modulation
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Summary:This paper presents a new space vector pulse width modulation (SVPWM) to eliminate common-mode voltage (CMV) for multilevel inverters. The proposed SVPWM is performed in a new coordinate system, in which the converter voltage vectors have only integer entries and the absolute coordinate increment between adjacent vectors is equal to 1. The location of the reference vector, detection of the nearest three CMV vectors, and duty cycles of the nearest three CMV vectors are all obtained by simple calculations, no lookup table is needed and the SVPWM is computationally fast. Compared with earlier pulse width modulations (PWMs), the realization of the CMV vectors is very simple, and the CMV of multilevel inverters are limited to zero with any modulation index. Because the SVPWM is independent of the level number of the inverter, the proposed SVPWM is suitable for any level of inverter. This paper also thoroughly compares the proposed SVPWM with prior PWMs. Experimental results are also given in the paper.
ISSN:1996-1073
1996-1073
DOI:10.3390/en10050715