A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s

• Published in: Journal of signal processing systems 2017-08, Vol.88 (2), p.107-125
• Main Authors: Maragos, Konstantinos, Spatharakis, Christos, Lentaris, George, Kontzilas, Panagiotis, Dris, Stefanos, Bakopoulos, Paraskevas, Avramopoulos, Hercules, Soudris, Dimitrios
• Format: Article
• Language: English
• Subjects: Circuits and Systems; Computer architecture; Computer Imaging; Customization; Data centers; Electrical Engineering; Engineering; Equalization; Equalizers; Field programmable gate arrays; Image Processing and Computer Vision; Interconnections; Links; Modulation; Optical communication; Optical interconnects; Optoelectronics; Pattern Recognition; Pattern Recognition and Graphics; Signal,Image and Speech Processing; Transceivers; Vision
• ISSN: 1939-8018; 1939-8115
• DOI: 10.1007/s11265-016-1201-y

Commodity optoelectronic components and multi-level modulation formats are combined nowadays in optical networks to increase their throughput while decreasing their cost. To overcome the inherent limitations of such interconnects, research focuses on digital equalizers that compensate for the effects of the developed channels. The current paper proposes the use of FPGAs to enhance the speed, power and flexibility of digital equalization for the next generation 100 Gb/s rack-to-rack optical links in datacenters. We present the high-performance hardware architecture of a flexible feed-forward equalizer (FFE) with multiple reconfigurations. We describe parallelization techniques to accelerate FFE, accuracy analysis for various FFE scenarios, as well as a design space exploration leading to a fine-tuned and platform-dependent FFE customization. Our final implementation on a single Xilinx XC7VH580T FPGA device with GTZ transceivers can support a single link of up to 112 Gbps (56 GSa/s with PAM-4 modulation) and 2.26⋅10 −6 Bit-Error-Rate.