A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-select (HS) disturbs in read and write cycles, at the expense of reduced cell read current (I CELL ) and degraded write margin (WM). This paper proposes the dual-split-control (DSC) scheme, including split...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2017-09, Vol.52 (9), p.2498-2514
Main Authors: Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Yi-Ju Chen, Yamauchi, Hiroyuki
Format: Article
Language:English
Subjects:
Circuit stability
Control stability
Electric potential
Layout
Low-voltage
MOS devices
read assist
SRAM
SRAM cells
Stability criteria
Strapping
Transistors
write assist
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Summary:Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-select (HS) disturbs in read and write cycles, at the expense of reduced cell read current (I CELL ) and degraded write margin (WM). This paper proposes the dual-split-control (DSC) scheme, including split WLs and split cell VSS (CVSS), for 6T SRAM to maintain a compact cell area and improve HS cell stability during the read and write cycles without degrading I CELL and WM. A segmented CVSS-strapping scheme is developed to suppress the ground bounce on the split-CVSS lines. The CVSS voltage for S6T can be generated by either a constant voltage source or a charge-sharing-based CVSS generation scheme. A 28-nm 256-kb DSC6T SRAM macro was fabricated and achieves a 280-mV lower VDDmin than a conventional 6T SRAM.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2017.2701547