Low power VLSI architecture design of BMC, BPSC and PC schemes

• Published in: Analog integrated circuits and signal processing 2017-10, Vol.93 (1), p.169-178
• Main Authors: Rajakumar, G., Andrew Roobert, A., Arun Samuel, T. S., Gracia Nirmala Rani, D.
• Format: Article
• Language: English
• Subjects: Circuits and Systems; Coding; Degeneration; Design modifications; Electrical Engineering; Engineering; Integrated circuits; Low level; MOS devices; Power consumption; Semiconductor devices; Signal,Image and Speech Processing; Transistors; Very large scale integration
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-017-1025-0

Line coding is used to tune the wave form based on the properties of the physical channel. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. The first objective of the proposed work is to design Generation and Degeneration operations of BMC, BPSC and PC techniques in a single chip. The second objective is to reduce the area and power consumption, by modifying the number of MOS devices used to design the system and by adjusting the width of the MOS devices. The proposed system is designed with 59 transistors and simulated using Cadence ® 90 nm technology. This occupies 1290 µm 2 . Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data has equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.