An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing

• Published in: Integration (Amsterdam) 2017-06, Vol.58, p.35-46
• Main Authors: Sheikh, Ahmad T., El-Maleh, Aiman H.
• Format: Article
• Language: English
• Subjects: Circuit reliability; Fault detection; Fault tolerance; Functionally redundant wire; Gates (circuits); Logic implications; Masking; Redundancy; Semiconductor devices; Single event transient (SET); Single event Upset (SEU); Sizing; Soft errors; Soft-error tolerance; System effectiveness; Transistors
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2017.01.005

With fabrication technology reaching nano levels, systems are exposed to higher susceptibility to soft errors. Thus, development of effective techniques for designing soft error tolerant systems is of high importance. In this work, an integrated soft error tolerance technique based on logical implications and transistor sizing is proposed. In order to reduce implication learning time, a set of source and target nodes with predefined thresholds are selected and implications between these nodes are extracted. Then, the impact of adding a functionally redundant wire (FRW) due to each implication is evaluated. This is done based on identifying an implication path and the gates along the implication path whose detection probabilities will be reduced due to adding the implication FRW. Then, the gain of an implication is estimated in terms of reduction in fault detection probabilities of gates along an implication path. The implication with the highest gain is selected. The process is repeated until the gain is less than a predetermined threshold. The proposed implication-based fault tolerance technique enhances the circuit reliability with minimal area overhead based on enhancing logical masking. However, its effectiveness depends on the existence of such relations in a circuit and can enhance circuit reliability upto a certain level. To enhance circuit reliability to any required level, selective-transistor redundancy (STR) based technique is then applied. This technique is based on providing fault tolerance for individual transistors with high detection probability based on transistor duplication and sizing. Experimental results show that the proposed integrated fault tolerance technique achieves similar reliability in comparison to applying STR alone with lower area overhead. •A method based on logical implications and transistor sizing is proposed.•Implications are extracted between a set of selected source and target nodes.•The impact of adding a functionally redundant wire due to each implication is done.•To enhance circuit reliability to any level, STR based technique is then applied.•The proposed integrated method achieves similar reliability as STR with lower area.