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PRO3: A hybrid NPU architecture
The PRO3 reduces the overhead incurred by common "brute-force" architectures by using the least-required hardware resources for certain common well-defined tasks.
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Published in: | IEEE MICRO 2004-09, Vol.24 (5), p.20 |
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Format: | Article |
Language: | English |
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container_issue | 5 |
container_start_page | 20 |
container_title | IEEE MICRO |
container_volume | 24 |
creator | Papaefstathiou, Ioannis Perissakis, Stylianos Orphanoudakis, Theofanis G Nikolaou, Nikos A |
description | The PRO3 reduces the overhead incurred by common "brute-force" architectures by using the least-required hardware resources for certain common well-defined tasks. |
doi_str_mv | 10.1109/MM.2004.55 |
format | article |
fullrecord | <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_journals_196370409</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>732768821</sourcerecordid><originalsourceid>FETCH-LOGICAL-p180t-30af84de0b4ca1ee13e473af534cc724c494e3d1bca2aa5981157a5ba1573593</originalsourceid><addsrcrecordid>eNotzU1PwkAQgOGNwcSCXPwDNt63zOzMul1vhPhBAkIMnMl0uw0QI7htD_57SfT03N5XqTuEAhH8ZLksDAAX1l6pDD05zcg0UBkYZzQ6Mjdq2LZHALAGykzdrz9W9JRP8_1PlQ51_r7e5pLC_tDF0PUp3qrrRj7bOP53pDYvz5vZm16sXuez6UKfsYROE0hTch2h4iAYI1JkR9JY4hCc4cCeI9VYBTEi1peI1omt5AJZTyP18Jc9p9N3H9tudzz16ety3KF_JAcMnn4B7XA8BA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>196370409</pqid></control><display><type>article</type><title>PRO3: A hybrid NPU architecture</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Papaefstathiou, Ioannis ; Perissakis, Stylianos ; Orphanoudakis, Theofanis G ; Nikolaou, Nikos A</creator><creatorcontrib>Papaefstathiou, Ioannis ; Perissakis, Stylianos ; Orphanoudakis, Theofanis G ; Nikolaou, Nikos A</creatorcontrib><description>The PRO3 reduces the overhead incurred by common "brute-force" architectures by using the least-required hardware resources for certain common well-defined tasks.</description><identifier>ISSN: 0272-1732</identifier><identifier>EISSN: 1937-4143</identifier><identifier>DOI: 10.1109/MM.2004.55</identifier><identifier>CODEN: IEMODZ</identifier><language>eng</language><publisher>Los Alamitos: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</publisher><subject>Computer architecture ; Information processing</subject><ispartof>IEEE MICRO, 2004-09, Vol.24 (5), p.20</ispartof><rights>Copyright Institute of Electrical and Electronics Engineers, Inc. (IEEE) Sep/Oct 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Papaefstathiou, Ioannis</creatorcontrib><creatorcontrib>Perissakis, Stylianos</creatorcontrib><creatorcontrib>Orphanoudakis, Theofanis G</creatorcontrib><creatorcontrib>Nikolaou, Nikos A</creatorcontrib><title>PRO3: A hybrid NPU architecture</title><title>IEEE MICRO</title><description>The PRO3 reduces the overhead incurred by common "brute-force" architectures by using the least-required hardware resources for certain common well-defined tasks.</description><subject>Computer architecture</subject><subject>Information processing</subject><issn>0272-1732</issn><issn>1937-4143</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><recordid>eNotzU1PwkAQgOGNwcSCXPwDNt63zOzMul1vhPhBAkIMnMl0uw0QI7htD_57SfT03N5XqTuEAhH8ZLksDAAX1l6pDD05zcg0UBkYZzQ6Mjdq2LZHALAGykzdrz9W9JRP8_1PlQ51_r7e5pLC_tDF0PUp3qrrRj7bOP53pDYvz5vZm16sXuez6UKfsYROE0hTch2h4iAYI1JkR9JY4hCc4cCeI9VYBTEi1peI1omt5AJZTyP18Jc9p9N3H9tudzz16ety3KF_JAcMnn4B7XA8BA</recordid><startdate>20040901</startdate><enddate>20040901</enddate><creator>Papaefstathiou, Ioannis</creator><creator>Perissakis, Stylianos</creator><creator>Orphanoudakis, Theofanis G</creator><creator>Nikolaou, Nikos A</creator><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20040901</creationdate><title>PRO3: A hybrid NPU architecture</title><author>Papaefstathiou, Ioannis ; Perissakis, Stylianos ; Orphanoudakis, Theofanis G ; Nikolaou, Nikos A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p180t-30af84de0b4ca1ee13e473af534cc724c494e3d1bca2aa5981157a5ba1573593</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Computer architecture</topic><topic>Information processing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Papaefstathiou, Ioannis</creatorcontrib><creatorcontrib>Perissakis, Stylianos</creatorcontrib><creatorcontrib>Orphanoudakis, Theofanis G</creatorcontrib><creatorcontrib>Nikolaou, Nikos A</creatorcontrib><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE MICRO</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Papaefstathiou, Ioannis</au><au>Perissakis, Stylianos</au><au>Orphanoudakis, Theofanis G</au><au>Nikolaou, Nikos A</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>PRO3: A hybrid NPU architecture</atitle><jtitle>IEEE MICRO</jtitle><date>2004-09-01</date><risdate>2004</risdate><volume>24</volume><issue>5</issue><spage>20</spage><pages>20-</pages><issn>0272-1732</issn><eissn>1937-4143</eissn><coden>IEMODZ</coden><abstract>The PRO3 reduces the overhead incurred by common "brute-force" architectures by using the least-required hardware resources for certain common well-defined tasks.</abstract><cop>Los Alamitos</cop><pub>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</pub><doi>10.1109/MM.2004.55</doi></addata></record> |
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identifier | ISSN: 0272-1732 |
ispartof | IEEE MICRO, 2004-09, Vol.24 (5), p.20 |
issn | 0272-1732 1937-4143 |
language | eng |
recordid | cdi_proquest_journals_196370409 |
source | IEEE Electronic Library (IEL) Journals |
subjects | Computer architecture Information processing |
title | PRO3: A hybrid NPU architecture |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T17%3A28%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=PRO3:%20A%20hybrid%20NPU%20architecture&rft.jtitle=IEEE%20MICRO&rft.au=Papaefstathiou,%20Ioannis&rft.date=2004-09-01&rft.volume=24&rft.issue=5&rft.spage=20&rft.pages=20-&rft.issn=0272-1732&rft.eissn=1937-4143&rft.coden=IEMODZ&rft_id=info:doi/10.1109/MM.2004.55&rft_dat=%3Cproquest%3E732768821%3C/proquest%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-p180t-30af84de0b4ca1ee13e473af534cc724c494e3d1bca2aa5981157a5ba1573593%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=196370409&rft_id=info:pmid/&rfr_iscdi=true |