A Task-centric Memory Model for Scalable Accelerator Architectures

This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory m...

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Bibliographic Details
Published in:IEEE MICRO 2010, Vol.30 (1), p.29
Main Authors: Kelm, John, Johnson, Daniel, Lumetta, Steven S., Frank, Matthew, Patel, Sanjay
Format: Article
Language:English
Subjects:
Cache
Computer architecture
Computer memory
Computer programming
Online Access:Get full text
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Summary:This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory model supports visual computing applications, which are becoming an important class of workloads capable of exploiting 1,000-core processors. [PUBLICATION ABSTRACT]
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2010.1