A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector

Programmability is one of the most significant advantages of a digital phase-locked loop (PLL) compared with a charge-pump PLL. In this paper, a digital PLL that extends programmability to include noise is introduced. A digitally controlled oscillator (DCO) using a switched capacitor for frequency f...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2018-01, Vol.53 (1), p.50-65
Main Authors: Taekwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Choo, Kyojin David, Sylvester, Dennis, Blaauw, David
Format: Article
Language:English
Subjects:
All-digital phase-locked loop (ADPLL)
Capacitors
Change detection
Charge pumps
clock generation
Figure of merit
Frequency locked loops
linearization
Mathematical model
Noise
noise reconfiguration
Phase locked loops
Phase locked systems
phase-locked loop (PLL)
Power consumption
switched capacitor
Switches
Transfer functions
Tuning
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Summary:Programmability is one of the most significant advantages of a digital phase-locked loop (PLL) compared with a charge-pump PLL. In this paper, a digital PLL that extends programmability to include noise is introduced. A digitally controlled oscillator (DCO) using a switched capacitor for frequency feedback is proposed to maintain a constant figure of merit while reconfiguring its noise performance. The proposed DCO offers an accurate and linear frequency tuning curve that is insensitive to environmental changes. A noise detection circuit using the statistical property of a bang-bang phase and frequency detector is proposed to autonomously adjust the output noise level depending on the noise specification. A prototype design is fabricated in a 28-nm FDSOI process. The integrated phase noise of the proposed PLL can be configured from 2.5 to 15 ps, while the power consumption ranges from 1.7 to 5 mW.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2017.2776313