A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscil...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2018-02, Vol.53 (2), p.470-483
Main Authors: Verbeke, Marijn, Rombouts, Pieter, Ramon, Hannes, Moeneclaey, Bart, Xin Yin, Bauwelinck, Johan, Torfs, Guy
Format: Article
Language:English
Subjects:
All-digital clock and data recovery (AD-CDR)
Analog circuits
CDR circuits
Clock recovery
Clocks
Computer architecture
Data recovery
Detectors
digital controlled oscillator (DCO)
digital loop filter (DLF)
Image edge detection
Inverse Alexander phase detector (PD)
Oscillators
Phase detectors
Phase frequency detector
Power consumption
Power demand
Receivers
subsampling
Synthesis
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Summary:Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm 2 and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5-25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2017.2755690