A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delt–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation

• Published in: IEEE journal of solid-state circuits 2018-01, Vol.53 (3), p.799
• Main Authors: Dey, Siladitya, Reddy, Karthikeyan, Mayaram, Kartikeya, Fiez, Terri S
• Format: Article
• Language: English
• Subjects: CMOS; Electric potential; Immunity; Linearity; Nonlinearity; Power consumption; Voltage controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2017.2777455

A two-stage continuous-time [Formula Omitted] modulator with voltage-controlled oscillator based quantizer (VCOQ) is presented. The presented modulator suppresses the VCOQ voltage-to-frequency nonlinearity through dual path cancellation to achieve high linearity. As an added advantage, this architecture exhibits strong immunity to the first stage quantization error leakage to the output due to gain mismatches between the two stages. Fabricated in a 65 nm CMOS technology, the prototype modulator operates at 1.5 GS/s and achieves 76.1 dB SNR, 73.5 dB SNDR, 88 dB SFDR, and 76.1 dB dynamic range (DR) in 50 MHz bandwidth. This prototype demonstrates robust performance with less than 1.5 dB variation in SNDR for ±10% gain mismatch between the two stages. Also, the SNDR variation remains within 1 dB for a temperature variation of 0°C–80°C. The modulator consumes 51.8 mW of power leading to a Walden FoM of 134 fJ/conv-step.