A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processo...

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Bibliographic Details
Published in:Scientific programming 2015-01, Vol.2015 (2015), p.1-16
Main Authors: Bin Ahmad, Maaz, Ziauddin, S. M., Taj, Imtiaz A., Asif, M., Tahir, M.
Format: Article
Language:English
Subjects:
Applications programs
Coding
Design
Electronic devices
Hardware
Image processing
Mobile computing
Multitasking
Pipelining (computers)
Power consumption
Processors
Software
Video
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Summary:One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB) level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.
ISSN:1058-9244
1875-919X
DOI:10.1155/2015/197843