Nanoscale Accumulated Body Si nMOSFETs

• Published in: IEEE transactions on electron devices 2018-04, Vol.65 (4), p.1283-1289
• Main Authors: Akbulut, Mustafa B., Dirisaglik, Faruk, Cywar, Adam, Faraclas, Azer, Pence, Douglas, Patel, Jyotica, Steen, Steven, Nunes, Ron W., Silva, Helena, Gokirmak, Ali
• Format: Article
• Language: English
• Subjects: Accumulation; Back biasing; Bias; CAD; Computer aided design; Computer simulation; Dielectrics; Fabrication; FETs; Field effect transistors; leakage currents; Logic gates; MOSFET; Semiconductor devices; Sensitivity; Silicon; silicon devices; Threshold voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2018.2809643

Narrow- and short-channel inversion-mode nMOSFETs with an accumulated body are experimentally demonstrated down to {W} \times {L} = \textsf {17} -nm \times37 -nm scale. Accumulation of holes on the p-type body is achieved by applying a negative bias on an independently controlled p+ polysilicon side-gate structure surrounding the FET body. Affecting the channel from two sides, electrical characteristics of the transistor can be modified, especially the threshold voltage ( {V} _{T} ). {V} _{T} sensitivity to the side-gate bias ( {V} _{\textsf {side}} ) shows a strong dependence on the device width for {W} < \textsf {40} nm, exponentially increasing to above 1 V/V for {W} = \textsf {17} nm. This sensitivity is significantly larger than what is predicted by 3-D Technology Computer Aided Design simulations. The devices exhibit very low leakage, good subthreshold slope, and improved drain-induced barrier lowering with the accumulation of the body.