Are the logical foundations of verifying compiler prototypes matching user expectations?

• Published in: Formal aspects of computing 2007-06, Vol.19 (2), p.139-158
• Main Author: CHALIN, Patrice
• Format: Article
• Language: English
• Subjects: Applied sciences; Computer science; control theory; systems; Exact sciences and technology; Global analysis, analysis on manifolds; Mathematics; Miscellaneous; Sciences and techniques of general use; Theoretical computing; Topology. Manifolds and cell complexes. Global analysis and analysis on manifolds
• ISSN: 0934-5043; 1433-299X
• DOI: 10.1007/s00165-006-0016-1

The verifying compiler (VC) project proposals suggest that mainstream software developers are its targeted end-users. Like other software engineering efforts, the VC project success depends on appropriate end-user consultation. Industrial use of program assertions for the purpose of run-time assertion checking (RAC) is becoming commonplace. A likely next step on the path to VC adoption is the use of assertions in extended static checking (ESC), a fully automated form of static program verification (SPV). Unfortunately, all current VC prototypes supporting SPV, adopt a semantics which is unsound relative to the standard run-time interpretation of assertions. In this article, we report on the results of a survey in which we asked industrial developers what logical semantics they want program assertions to have, and whether consistency across RAC and SPV tools is important. Survey results indicate that developers are in favor of a semantics for assertions that is compatible with their current use in RAC.