On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO^sub 2^ for energy efficient sub-0.2 V operation

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate sta...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 2018-02, Vol.57 (2), p.024201
Main Authors: Jang, Kyungmin, Saraya, Takuya, Kobayashi, Masaharu, Hiramoto, Toshiro
Format: Article
Language:English
Subjects:
Capacitance
CMOS
Computer simulation
Energy efficiency
Ferroelectric materials
Ferroelectricity
Hafnium oxide
Mathematical models
Power efficiency
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Summary:We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.
ISSN:0021-4922
1347-4065