Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos

• Published in: Expert systems with applications 2018-07, Vol.101, p.159-175
• Main Authors: Mukherjee, Rohan, Saha, Priyabrata, Chakrabarti, Indrajit, Dutta, Pranab Kumar, Ray, Ajoy Kumar
• Format: Article
• Language: English
• Subjects: Adaptive algorithms; Adaptive search algorithm; Adaptive search techniques; Adaptive systems; Algorithms; Camcorders; Codec; Data re-use; Digital media; Electronic devices; Fast motion estimation; Frames (data processing); Hardware; High definition; Hydraulics; Integrated circuits; Motion control; Motion simulation; Novel memory organization; Numerical analysis; Parallel processing; Portable equipment; Power consumption; Searching; Smartphones; Software; Very large scale integration; VLSI architecture
• ISSN: 0957-4174; 1873-6793
• DOI: 10.1016/j.eswa.2018.02.020

•Adaptive motion estimation algorithm and VLSI design that can process HD frames.•The algorithm exploits the considerable correlation within neighboring macroblocks.•VLSI design generates adaptive pattern and uses interleaved memory organization.•Working at 243 MHz, the design can process 66 HD (1280 × 720) frames per second.•The design consumes an area of 38.2 K gate equivalent and 36 mW of dynamic power. Motion estimation (ME) plays an important part in the functioning of the video codec by identifying and reducing the temporal redundancies in between successive frames of a video sequence. Block matching algorithm (BMA) has been accepted as one of the finest approaches for motion estimation due to its efficiency and ease of implementation. This paper presents a new and improved iterative and adaptive search strategy for block-based motion estimation along with its efficient hardware implementation. Since it is expected that there will be more demand for streaming video services on mobile devices, designing fine tuning algorithm with dedicated efficient hardware would provide significant benefits. The present motion estimation algorithm is adaptive in nature that takes into consideration the motion content of the current frame while predicting the motion vector. The adaptive nature of the search eases the complexity of motion estimation and the algorithm makes use of the correlation present among the motion vectors of the neighboring blocks to lower the number of search position. Traditionally, such adaptive algorithms are executed by CPU cores running a software stack. Since software involves a significant amount of overheads like fetching into cache, branches, stalls etc., the efficiency of the proposed algorithm can be overshadowed by the hardware platform. To avoid this, compact hardware architecture was developed which stands ahead of other existing architectures as shown in comparison. The VLSI design for the proposed algorithm presented in this work deals with the generation of the adaptive search pattern and use of interleaved memory organization fasten the operational speed. A profitable data re-use scheme and involvement of minimum processing elements required for parallelization reduce the on-chip area. Working at a frequency of 243 MHz, the proposed design can process 66 720p HD (1280 × 720) frames in one second consuming an area of 38.2 K gate equivalent. Hence, the proposed design can be incorporated in video codecs to be used in commercial