Power Management of Wideband Code Division Multiple Access RF Power Amplifiers With Antenna Mismatch

• Published in: IEEE transactions on power electronics 2010-04, Vol.25 (4), p.981-991
• Main Authors: Paul, Rajarshi, Sankey, Luke, Corradini, Luca, Popovic, Zoya, Maksimovic, Dragan
• Format: Article
• Language: English
• Subjects: Adaptive arrays; Adaptive systems; Antennas; Broadband amplifiers; Broadband antennas; Code Division Multiple Access; Digital controller; Dynamical systems; Electric potential; Electronics; Energy management; Impedance; Multiaccess communication; noninverting buck-boost power converter; Power amplifiers; Power management; Power supplies; Radio frequencies; Radio frequency; Radio frequency identification; Radiofrequency amplifiers; RF impedance tuner; RF power amplifier (RFPA); sigma-delta (Σ-Δ) modulator; Voltage
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2009.2036355

This paper focuses on a combination of adaptive power supply and adaptive impedance tuning for WCDMA RF power amplifiers (RFPA) in wireless handsets in order to improve the system efficiency under different transmit power levels and antenna mismatch. The adaptive power supply is a noninverting buck-boost power converter. It is shown that precise output voltage positioning and low output voltage ripple over a wide output voltage range, including buck, boost, and buck/boost transition modes, can be accomplished using ¿-¿ modulation in combination with a small, low-resolution DPWM core. A two-mode digital controller is presented, in which the compensator parameters are changed upon buck/boost mode transitions in order to improve closed-loop dynamic performance. Furthermore, improvements in system efficiency are demonstrated using this adaptive power supply combined with an adaptive RF impedance tuner between the RFPA and the antenna. The results are verified on an experimental test bed that consists of a discrete RFPA, impedance tuner, a prototype 0.5 ¿m CMOS power stage IC that integrates power MOSFETs, drivers and deadtime control logic, and a digital power management controller implemented on an FPGA.