High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm

This paper proposes a new architecture of 2-D block FIR filter using distributed arithmetic (DA) algorithm, which is known for the efficient design of multiply and accumulate block. Hardware-based architecture is proposed for DA lookup table (DA-LUT) that makes the architecture of 2-D FIR filter rec...

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Bibliographic Details
Published in:Circuits, systems, and signal processing systems, and signal processing, 2019-03, Vol.38 (3), p.1099-1113
Main Authors: Kumar, Prashant, Shrivastava, Prabhat Chandra, Tiwari, Manish, Mishra, Ganga Ram
Format: Article
Language:English
Subjects:
Algorithms
Arithmetic
Circuits and Systems
Complexity
Design
Electrical Engineering
Electronics and Microelectronics
Engineering
FIR filters
Hardware
Instrumentation
Signal,Image and Speech Processing
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Summary:This paper proposes a new architecture of 2-D block FIR filter using distributed arithmetic (DA) algorithm, which is known for the efficient design of multiply and accumulate block. Hardware-based architecture is proposed for DA lookup table (DA-LUT) that makes the architecture of 2-D FIR filter reconfigurable. Further, due to block processing, sharing takes place among DA-LUTs at various stages. Thus, a common DA-LUT may be designed for block inputs which reduce the hardware complexity for DA-LUT. Furthermore, memory overlapping is used to reduce the systolic architectures in proposed design over existing designs. For higher-order 2-D FIR filter, the complexity of DA-LUT is reduced by dividing the internal block into parallel and small blocks. With the help of ASIC synthesis results, a comparative analysis of proposed design with the earlier reported designs is presented, and it is shown that the proposed design leads to significant improvements in various performance parameters.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-018-0897-2