A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

• Published in: arXiv.org 2013-09
• Main Authors: Oberla, E, J -F Genat, Grabas, H, Frisch, H, Nishimura, K, Varner, G
• Format: Article
• Language: English
• Subjects: Bandwidths; Channels; Circuit design; CMOS; Digitization; Dynamic range; Feature extraction; Integrated circuits; Linearity; Nonlinearity; Power consumption; Recording; Sampling; Servocontrol; Subtraction; Vibration; Waveforms
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.1309.4397

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available.The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.