Electro‐Physical Properties of Gate‐Last Silicon MOSFETs with Low‐Temperature SiOxNy/HfOx Stack After Ultra‐Shallow Fluorine Implantation from RF Plasma

Ultra‐shallow fluorine implantation from radio frequency (RF) plasma performed in reactive ion etching (RIE) reactor at room temperature (RT) is adopted to metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) technology on silicon (Si) substrates with gate‐last low‐temperature SiOxNy/HfOx do...

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Bibliographic Details
Published in:Physica status solidi. PSS-RRL. Rapid research letters 2018-08, Vol.12 (8), p.n/a
Main Authors: Mroczyński, Robert, Jasiński, Jakub
Format: Article
Language:English
Subjects:
Charge density
electrical characterization
Electrical properties
Fluorine
fluorine implantation
high‐k dielectrics
Implantation
Ion etching
Low temperature
MOSFETs
PECVD
Physical properties
Radio frequency
Reactive ion etching
reactive magnetron sputtering
Semiconductor devices
Silicon substrates
Transistors
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Summary:Ultra‐shallow fluorine implantation from radio frequency (RF) plasma performed in reactive ion etching (RIE) reactor at room temperature (RT) is adopted to metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) technology on silicon (Si) substrates with gate‐last low‐temperature SiOxNy/HfOx double‐gate dielectric stack. The implantation technology is optimized in order to get the maximum fluorine concentration very close to the silicon sub‐surface region. The electrical characterization of fabricated structures reveals an improved quality of the semiconductor/dielectric interface, i.e., lower interface state density (Nit), effective charge (Qeff) and, as a consequence, enhanced mobility (μeff) value and lower sub‐threshold swing (SS) of the investigated MOSFETs. The presented findings are promising for possible applications of fluorine implantation from RF plasma in modern semiconductor devices. This study presents the feasibility of ultra‐shallow fluorine implantation into silicon sub‐surface region performed in the standard reactive ion etching (RIE) process. The implantation is adopted to the MOSFETs technology with gate‐last SiOxNy/HfOx double‐gate dielectric stacks. An improved quality of fabricated structures has been observed that makes the RIE implantation a very favorable option for a controllable and repeatable introduction of fluorine ions into Si substrate.
ISSN:1862-6254
1862-6270
DOI:10.1002/pssr.201800152