Etch process modules development and integration in 3D-SOC applications

• Published in: Microelectronic engineering 2018-09, Vol.196, p.38-48
• Main Authors: Tutunjyan, Nina, Sardo, Stefano, De Vos, Joeri, Van Huylenbroeck, Stefaan, Jourdain, Anne, Peng, Lan, Inoue, Fumihiro, Rassoul, Nouredine, Beyer, Gerald, Beyne, Eric, Miller, Andy, Piumi, Daniele
• Format: Article
• Language: English
• Subjects: 3-D technology; 3D System-On-Chip (3D-SOC); Bonding; Deep Silicon Etch; Dielectric properties; DSiE; Electrical properties; Electron etching; Material properties; Modules; Moore's law; Semiconductors; Silicon wafers; Through Silicon Vias (TSV) last; wafer thinning; Wafer-to-Wafer (W2W) bonding
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2018.04.019

Since the challenges of maintaining the Moore's law - through traditional dimensional scaling or exploiting new materials properties - are becoming increasingly difficult, 3D integration technologies are gaining more and more attention and importance. At system level 3D-SOC solutions are of great interest, in particular those obtained through Wafer-to-Wafer (W2W) bonding due to superior overlay performance. In this paper we present the development of etch process modules for fine pitch via last interconnects realized on wafers with dielectric bonding and their integration in a packaging test chip, followed by electrical characterization. [Display omitted] •Dual depth TSV’s integration scheme for 3D SOC requires the development of several etch modules.•Wafer thinning, top dielectric etch/DSiE, STI/PMD/bonding stack and liner etch modules have been developed and integrated.•Electrical results of test structures for 1x5um TSV’s show more than 80% yield.•This concept has been demonstrated successfully also on higher AR: 2x20um TSV’s.•High density TSV last approach for 3D SOC applications has been achieved.