Power optimized programmable embedded controller

Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating tec...

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Published in:arXiv.org 2010-09
Main Authors: Kamaraju, M, K Lal Kishore, Tilak, A V N
Format: Article
Language:English
Subjects:
Architecture
Control systems design
Controllers
Hardware description languages
Microprocessors
Portable equipment
Power consumption
Programmable controllers
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K Lal Kishore
Tilak, A V N
description Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.
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fullrecord <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_journals_2087096971</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2087096971</sourcerecordid><originalsourceid>FETCH-LOGICAL-a511-419e50285f584d1d948fe7dac9c49c9a83e04e35c65aa98c4b9fb911d856c1403</originalsourceid><addsrcrecordid>eNotjs9Lw0AQRhdBsNTePQY8J87s7iQ7Ryn-goIeei-b3YmkJN26SVX86y3o6YN3eO9T6gahso4I7nz-7j8rBOAKG64v1EIbg6WzWl-p1TTtAUDXjSYyCwVv6UtykY5zP_Y_EotjTu_Zj6NvBylkbCXGMw3pMOc0DJKv1WXnh0lW_7tU28eH7fq53Lw-vazvN6UnxNIiC4F21JGzESNb10kTfeBgObB3RsCKoVCT9-yCbblrGTE6qgNaMEt1-6c9__k4yTTv9umUD-fiToNrgGtu0PwCQYpFEw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2087096971</pqid></control><display><type>article</type><title>Power optimized programmable embedded controller</title><source>Publicly Available Content Database</source><creator>Kamaraju, M ; K Lal Kishore ; Tilak, A V N</creator><creatorcontrib>Kamaraju, M ; K Lal Kishore ; Tilak, A V N</creatorcontrib><description>Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.</description><identifier>EISSN: 2331-8422</identifier><identifier>DOI: 10.48550/arxiv.1009.1796</identifier><language>eng</language><publisher>Ithaca: Cornell University Library, arXiv.org</publisher><subject>Architecture ; Control systems design ; Controllers ; Hardware description languages ; Microprocessors ; Portable equipment ; Power consumption ; Programmable controllers</subject><ispartof>arXiv.org, 2010-09</ispartof><rights>2010. This work is published under http://arxiv.org/licenses/nonexclusive-distrib/1.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.proquest.com/docview/2087096971?pq-origsite=primo$$EHTML$$P50$$Gproquest$$Hfree_for_read</linktohtml><link.rule.ids>776,780,25731,27902,36989,44566</link.rule.ids></links><search><creatorcontrib>Kamaraju, M</creatorcontrib><creatorcontrib>K Lal Kishore</creatorcontrib><creatorcontrib>Tilak, A V N</creatorcontrib><title>Power optimized programmable embedded controller</title><title>arXiv.org</title><description>Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.</description><subject>Architecture</subject><subject>Control systems design</subject><subject>Controllers</subject><subject>Hardware description languages</subject><subject>Microprocessors</subject><subject>Portable equipment</subject><subject>Power consumption</subject><subject>Programmable controllers</subject><issn>2331-8422</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><sourceid>PIMPY</sourceid><recordid>eNotjs9Lw0AQRhdBsNTePQY8J87s7iQ7Ryn-goIeei-b3YmkJN26SVX86y3o6YN3eO9T6gahso4I7nz-7j8rBOAKG64v1EIbg6WzWl-p1TTtAUDXjSYyCwVv6UtykY5zP_Y_EotjTu_Zj6NvBylkbCXGMw3pMOc0DJKv1WXnh0lW_7tU28eH7fq53Lw-vazvN6UnxNIiC4F21JGzESNb10kTfeBgObB3RsCKoVCT9-yCbblrGTE6qgNaMEt1-6c9__k4yTTv9umUD-fiToNrgGtu0PwCQYpFEw</recordid><startdate>20100909</startdate><enddate>20100909</enddate><creator>Kamaraju, M</creator><creator>K Lal Kishore</creator><creator>Tilak, A V N</creator><general>Cornell University Library, arXiv.org</general><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>L6V</scope><scope>M7S</scope><scope>PHGZM</scope><scope>PHGZT</scope><scope>PIMPY</scope><scope>PKEHL</scope><scope>PQEST</scope><scope>PQGLB</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope></search><sort><creationdate>20100909</creationdate><title>Power optimized programmable embedded controller</title><author>Kamaraju, M ; K Lal Kishore ; Tilak, A V N</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a511-419e50285f584d1d948fe7dac9c49c9a83e04e35c65aa98c4b9fb911d856c1403</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Architecture</topic><topic>Control systems design</topic><topic>Controllers</topic><topic>Hardware description languages</topic><topic>Microprocessors</topic><topic>Portable equipment</topic><topic>Power consumption</topic><topic>Programmable controllers</topic><toplevel>online_resources</toplevel><creatorcontrib>Kamaraju, M</creatorcontrib><creatorcontrib>K Lal Kishore</creatorcontrib><creatorcontrib>Tilak, A V N</creatorcontrib><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science &amp; Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection (ProQuest)</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Engineering Collection</collection><collection>Engineering Database</collection><collection>ProQuest Central (New)</collection><collection>ProQuest One Academic (New)</collection><collection>Publicly Available Content Database</collection><collection>ProQuest One Academic Middle East (New)</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Applied &amp; Life Sciences</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><jtitle>arXiv.org</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kamaraju, M</au><au>K Lal Kishore</au><au>Tilak, A V N</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Power optimized programmable embedded controller</atitle><jtitle>arXiv.org</jtitle><date>2010-09-09</date><risdate>2010</risdate><eissn>2331-8422</eissn><abstract>Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.</abstract><cop>Ithaca</cop><pub>Cornell University Library, arXiv.org</pub><doi>10.48550/arxiv.1009.1796</doi><oa>free_for_read</oa></addata></record>
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subjects Architecture
Control systems design
Controllers
Hardware description languages
Microprocessors
Portable equipment
Power consumption
Programmable controllers
title Power optimized programmable embedded controller
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-24T00%3A11%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Power%20optimized%20programmable%20embedded%20controller&rft.jtitle=arXiv.org&rft.au=Kamaraju,%20M&rft.date=2010-09-09&rft.eissn=2331-8422&rft_id=info:doi/10.48550/arxiv.1009.1796&rft_dat=%3Cproquest%3E2087096971%3C/proquest%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-a511-419e50285f584d1d948fe7dac9c49c9a83e04e35c65aa98c4b9fb911d856c1403%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=2087096971&rft_id=info:pmid/&rfr_iscdi=true