Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design

To improve leakage power along with better cell stability, a 10 T SRAM cell is presented in this paper. Further, the proposed cell is used to implement a 6-input look up table (LUT) of FPGA and a 2 kb SRAM macroblock. The proposed cell achieves better results in terms of write static noise margin by...

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Bibliographic Details
Published in:Integration (Amsterdam) 2018-06, Vol.62, p.1-13
Main Authors: Singh, P., Reniwal, B.S., Vijayvargiya, V., Sharma, V., Vishvakarma, S.K.
Format: Article
Language:English
Subjects:
Control stability
Feedback control systems
FPGA
Leakage
Leakage power
LUT
Parameter identification
Portable equipment
Positive feedback
Semiconductors
SRAM
Static noise margin (SNM)
Systems stability
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Summary:To improve leakage power along with better cell stability, a 10 T SRAM cell is presented in this paper. Further, the proposed cell is used to implement a 6-input look up table (LUT) of FPGA and a 2 kb SRAM macroblock. The proposed cell achieves better results in terms of write static noise margin by 1.66 × , 1.8 × ; read static noise margin by 3.8 × , 1.37 × ; write trip point by 2 × , 2 × as compared to conventional (C) 6 T, read decoupled (RD) 8 T SRAM, respectively. The leakage power is also reduced to 0.07 × , and 0.43 × as compared C6T and RD8T SRAM, respectively at 0.3 V VDD. •Ultra low power SRAM cell for look up table (LUT) of FPGA.•High read, write and hold static noise margins.•Low leakage power.•High Ion current.•Better performance at different process corners.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2018.03.006