The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs

• Published in: International journal of parallel programming 2018-08, Vol.46 (4), p.722-735
• Main Authors: Liu, Wenjie, Ma, Sheng, Huang, Libo, Wang, Zhiying
• Format: Article
• Language: English
• Subjects: Computer memory; Computer Science; Connectivity; Controllers; Efficiency; Energy efficiency; Power consumption; Processor Architectures; Scheduling; Servers; Software Engineering/Programming and Operating Systems; Special issue on Network and Parallel Computing for New Architectures and Applications; Theory of Computation; Weight reduction
• ISSN: 0885-7458; 1573-7640
• DOI: 10.1007/s10766-017-0521-2

Memory access scheduling schemes, often performed in memory controllers, have a marked impact on alleviating the heavy burden placed on memory systems of GPGPUs. Existing out-of-order scheduling schemes, like FR-FCFS, improve memory access efficiency by reordering memory request sequences at the destination. Their effectiveness, however, is at the expense of complex logics and high power consumption. In this paper, we propose a NoC-side memory access scheduling based on the key insight that the transmission of on-chip networks is the dominating factor in destroying the row access locality and causing poor memory access efficiency. With appropriate NoC-side optimization, the straight-forward in-order scheduling can be used in memory controllers to simplify scheduling logics and alleviate the tight power envelope. Moreover, we introduce several light-weight optimizations to further improve the system performance. Experimental results on memory-intensive applications show that, comparing with FR-FCFS, our proposed scheme increases the overall system performance by 10.5%, reduces the power consumption by 20% and improves the energy efficiency by 36.9%.