Instruction Fetch Energy Reduction with Biased SRAMs

Especially in programmable processors, energy consumption of integrated memories can become a limiting design factor due to thermal dissipation power constraints and limited battery capacity. Consequently, contemporary improvement efforts on memory technologies are focusing more on the energy-effici...

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Bibliographic Details
Published in:Journal of signal processing systems 2018-11, Vol.90 (11), p.1519-1532
Main Authors: Multanen, Joonas, Viitanen, Timo, Jääskeläinen, Pekka, Takala, Jarmo
Format: Article
Language:English
Subjects:
Batteries
Circuits and Systems
CMOS
Computer Imaging
Design factors
Dissipation factor
Efficiency
Electrical Engineering
Energy consumption
Energy dissipation
Energy management
Engineering
Image Processing and Computer Vision
Masking
Masks
Pattern Recognition
Pattern Recognition and Graphics
Power efficiency
Power management
Signal,Image and Speech Processing
Static random access memory
Vision
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Summary:Especially in programmable processors, energy consumption of integrated memories can become a limiting design factor due to thermal dissipation power constraints and limited battery capacity. Consequently, contemporary improvement efforts on memory technologies are focusing more on the energy-efficiency aspects, which has resulted in biased CMOS SRAM cells that increase energy efficiency by favoring one logical value over another. In this paper, xor-masking, a method for exploiting such contemporary low power SRAM memories is proposed to improve the energy-efficiency of instruction fetching. Xor-masking utilizes static program analysis statistics to produce optimal encoding masks to reduce the occurrence of the more energy consuming instruction bit values in the fetched instructions. The method is evaluated on LatticeMico32, a small RISC core popular in ultra low power designs, and on a wide instruction word high performance low power DSP. Compared to the previous “bus invert” technique typically used with similar SRAMs, the proposed method reduces instruction read energy consumption of the LatticeMico32 by up to 13% and 38% on the DSP core.
ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-018-1367-6