A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delt–Sigma Modulator Using Source-Follower-Based Integrators

• Published in: IEEE journal of solid-state circuits 2018-01, Vol.53 (10), p.2772
• Main Authors: Kwak, Yong-Sik, Kang-Il Cho, Ho-Jin, Kim, Seung-Hoon, Lee, Gil-Cho, Ahn
• Format: Article
• Language: English
• Subjects: CMOS; Comparators; Digital to analog conversion; Digital to analog converters; Distortion; Integrators; Linearity; Noise; Noise levels; Power consumption; Signal processing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2859401

This paper presents a 2-2 discrete-time (DT) resolution-enhanced sturdy multi-stage noise-shaping (SMASH) delt–sigma modulator. It uses source-follower-based integrators to efficiently increase the operating speed of a DT modulator. A SMASH topology that consists of two second-order low-distortion feed-forward stages provides an enhanced linearity by reducing the sensitivity to the non-ideal gain and distortion of the proposed integrator. The resolution of the proposed SMASH architecture is improved by eliminating the first-stage quantization noise from the output. In order to reduce power and area of the modulator, one 5-bit feedback digital-to-analog converter is shared for both stages, and the number of comparators for a 4-bit quantizer in the second stage is reduced by scaling the signal swing range. The prototype delt–sigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB signal-to-noise-and-distortion ratio (SNDR) in a 20-MHz bandwidth. From a 1.2-V supply voltage operating at a 500-MHz clock frequency, the total power consumption of the prototype modulator is 20.4 mW, corresponding to a Walden and Schreier figure of merits of 141.3 fJ/conversion-step and 165.7 dB, respectively.