One electron-controlled multiple-valued dynamic random-access-memory

We propose a new architecture for a dynamic random-access-memory (DRAM) capable of storing multiple values by using a single-electron transistor (SET). The gate of a SET is designed to be connected to a plurality of DRAM unit cells that are arrayed at intersections of word lines and bitlines. In thi...

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Bibliographic Details
Published in:AIP advances 2016-02, Vol.6 (2), p.025320-025320-5
Main Authors: Kye, H. W., Song, B. N., Lee, S. E., Kim, J. S., Shin, S. J., Choi, J. B., Yu, Y.-S., Takahashi, Y.
Format: Article
Language:English
Subjects:
Access control
Intersections
Power consumption
Random access memory
Single-electron transistors
Storage
Unit cell
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Summary:We propose a new architecture for a dynamic random-access-memory (DRAM) capable of storing multiple values by using a single-electron transistor (SET). The gate of a SET is designed to be connected to a plurality of DRAM unit cells that are arrayed at intersections of word lines and bitlines. In this SET-DRAM hybrid scheme, the multiple switching characteristics of SET enables multiple value data stored in a DRAM unit cell, and this increases the storage functionality of the device. Moreover, since refreshing data requires only a small amount of SET driving current, this enables device operating with low standby power consumption.
ISSN:2158-3226
2158-3226
DOI:10.1063/1.4942901