Crystalline ZrTiO4 gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

• Published in: Applied physics letters 2015-02, Vol.106 (5)
• Main Authors: Wu, Chao-Yi, Hsieh, Ching-Heng, Lee, Ching-Wei, Wu, Yung-Hsien
• Format: Article
• Language: English
• Subjects: Annealing; Applied physics; Crystallization; Equivalence; Field effect transistors; Hole mobility; MOSFETs; Reliability analysis; Semiconductor devices; Silicon substrates; Stability; Stability analysis; Surface roughness; Threshold voltage; Yttrium oxide
• ISSN: 0003-6951; 1077-3118
• DOI: 10.1063/1.4907728

ZrTiO4 crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb2O3 interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (Dit) of 2.75 × 1011 cm−2eV−1 near the midgap and low oxide traps. Crystallization of ZrTiO4 and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low Dit value and small EOT. Owing to the Y2O3 interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm2/V-s at 1 MV/cm. In addition, Ion/Ioff ratio larger than 106 is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb2O3/o-ZrTiO4 gate stack holds the great potential for next-generation electronics.