Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) a...

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Bibliographic Details
Published in:Applied physics letters 2014-03, Vol.104 (9)
Main Authors: Biswas, Arnab, Dagtekin, Nilay, Grabinski, Wladyslaw, Bazigos, Antonios, Le Royer, Cyrille, Hartmann, Jean-Michel, Tabone, Claude, Vinet, Maud, Ionescu, Adrian M.
Format: Article
Language:English
Subjects:
Applied physics
Computer memory
Dynamic random access memory
Field effect transistors
Random access memory
Semiconductor devices
Transistors
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Summary:In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.
ISSN:0003-6951
1077-3118
DOI:10.1063/1.4867527