A 14-bit 250 kS/s two-step inverter-based incremental Σ Δ ADC for CMOS image sensor in 0.18 μ m technology

This paper presents a 14-bit Incremental Sigma-Delta (ΣΔ) analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same ΣΔ modulator is used for both steps, the overall complexity is reduced. F...

Full description

Saved in:
Bibliographic Details
Published in:Analog integrated circuits and signal processing 2018-01, Vol.97 (3), p.427-435
Main Authors: Bisiaux, Pierre, Lelandais-Perrault, Caroline, Kolar, Anthony, Filipe Vinci dos Santos, Benabes, Philippe
Format: Article
Language:English
Subjects:
Analog to digital conversion
Analog to digital converters
CMOS
Digital cameras
Digital imaging
Inverters
Operational amplifiers
Oversampling
Power consumption
Technology
Transconductance
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a 14-bit Incremental Sigma-Delta (ΣΔ) analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same ΣΔ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in 0.18μm CMOS technology. The simulation is performed with a 1.8 V voltage supply, a 20 MHz system clock frequency and an oversampling ratio (OSR) of 70, and achieves a power consumption is 460μW, a SNDR of 85.4 dB at a sampling rate of 250 kS/s.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-018-1238-x